Microprocessors are constantly evolving with the advent of new technologies in order to meet the requirements of more complex and computation hungry applications. The problem of misprediction in branches is one of the key issues as the complexity of the microprocessor increases. Increase in misprediction leads to increase in clock cycles adding latency and reducing the overall performance of the processor. Instruction level parallelism requires branch predictor to reduce number of stalls n hence, waiting time. This leads to designing efficient branch predictors to avoid the branch misprediction penalties in order to improve performance in terms of speed and power usage. In this survey, we will analyze existing branch prediction techniques and compare their strengths and weaknesses in comparison with each other.
Volume V Iseue II Paper IV Daneben ist sydney auch sitz eines anglikanischen und eines katholischen erzbischofs.